It is well-known that a peak in the electric field at the drain edge of the gate contact can limit the breakdown voltage of field effect transistors (FETs). In GaN FETs, the high electric fields in this region also commonly result in electron trapping at surface states and/or in the buffer, barrier, or passivation layers of the device, resulting in a virtual gate and reducing the on-state current of the device during high-voltage dynamic operation (known as “current collapse” or increased dynamic on-resistance). These issues can be mitigated through the use of field plates, which distribute the electric field over a larger area in the gate-drain region of the device, therefore reducing the peak field intensity.
In the prior art high-voltage GaN devices have typically utilized either a gate with a single field plate or multiple gate or source connected field plates separated by supporting dielectric layers, requiring multiple metallization steps during processing.
Y. F. Wu et al. describe in “30-W/mm GaN HEMTs by Field Plate Optimization”, IEEE Electron Device Letters, Vol. 25, No. 3 (2004), a single gate-connected field-plate FET. The disadvantages of this approach include a non-optimum electric field profile due to having only a single field plate, and a requirement for multiple metallization steps.
Saito et al. describe in “High Breakdown Voltage AlGaN—GaN Power-HEMT Design and High Current Density Switching Behavior”, IEEE Transactions on Electronic Devices, Vol. 50, No. 12 (2003) a single source-connected field plate FET. Field plate design and optimization are limited in this approach due to the single field-plate and discontinuity between gate and field-plate, resulting in a non-optimal electric field profile.
Y. Dora et al. describe in “High Breakdown Voltage Achieved on AlGaN/GaN HEMTs With Integrated Slant Field Plates”, IEEE Electron Device Letters, Vol. 27, No. 9 (2006) a slanted gate field plate to reduce the peak electric field in the device. The disadvantages of this approach include a symmetric gate profile, which increases parasitic Cgs and limits the source-gate spacing, and poor process control over slant gate angle and gate length.
H. Xing et al. describe in “High Breakdown Voltage AlGaN—GaN HEMTs Achieved by Multiple Field Plates”, IEEE Electron Device Letters, Vol. 25, No. 4 (2004) a multiple gate-connected field plate structure. The disadvantages of this approach include separation between the field plates by supporting dielectric layers, which limits field plate design and results in non-optimum electric field profile, multiple metallization steps, and non-plated gate and field plates.
Wu et al. describe in “Wide bandgap transistors with multiple field plates”, U.S. Published Patent Application 2009/0267116 several multiple-field-plate GaN FET designs with gate and source-connected field plates separated by supporting dielectric layers. The disadvantages of these approaches include a separation between the field plates by supporting dielectric layers, which limits field plate design and results in non-optimum electric field profile, multiple metallization steps, and non-plated gate and field plates.
Parikh et al. describe in “Wide bandgap transistor devices with field plates” U.S. Pat. No. 7,501,669 issued Mar. 10, 2009, a stepped gate field-plate structure, as shown in FIG. 7 of the Patent. However Parikh does not describe a method of fabrication.
What is needed is a stepped field plate for a field-effect transistor and method of making the stepped field plate that does not have the disadvantages of the prior art. The embodiments of the present disclosure answer these and other needs.